As the complexity of integrated circuits continues to increase, new approaches for testing such integrated circuits are constantly being developed. These approaches include the design and use of circuitry that is specifically designed for testing the integrated circuit in which it is implemented. One such approach that is widely used is the use of an Institute for Electrical and Electronics Engineers (IEEE) 1149.1 Standard Joint Test Action Group (JTAG) Test Access Port (TAP) controller. Such TAP controllers are implemented using a sixteen state, state machine to execute various instructions related to verifying functionality of a circuit in which the TAP controller is implemented.
At the component level, a TAP port is operated using five device pins (e.g., accessible at the packages pins). A TAP controller's pins include a Test Data In (TDI) pin, a Test Mode Select (TMS) pin, a Test Clock (TCK) pin, a Test Data Output (TDO) pin and a Test Reset (TRST) pin. During functional testing at the component level, accessing the TAP controller pins is easily accomplished. However, once a component is mounted, for example, on a system board, accessing the TAP controller requires that the TAP controller pins be routed on the board so that a user wishing to use the TAP port has access to them. Such routing may increase system board complexity and cost. Further, having board level access to a given component's TAP controller is of essentially no value to end consumers. Therefore, the cost of providing board level access to TAP controllers of devices on a system board is not value added for end consumers. Furthermore, operating a TAP controller in such a fashion (e.g., in a system board) typically requires complicated serial programming, including monitoring the state of a TAP controller that is being accessed at the system board level.